[Hackrf-dev] My code for Si5351 configuration, LPC clock tree configuration, bit-banding functions

[Jared Boone]

On Jun 6, 2012, at 6:57 PM, Michael Ossmann <mike at ossmann.com> wrote:


> Is there a reason you configured PLL1 in multiple stages?  Can I just

> configure it to 17x and enable?


No. When I tried that, it would Hard Fault, unless I was debugging (which I guess gives the PLL time to stabilize). I observed in the NXP examples that they did it in stages, which I emulated, and which immediately fixed the problem. You can experiment for yourself and see if you have the same problem going straight to 17x.

        - Jared