[Hackrf-dev] rebuild sgpio_if/top.vhd to get new cpld image

[Louie lu]

Hi guys,
I am new here and also new to hackrf one.
A few months back I bought a hackrf one myself. It is an excellent device. After spending some time on it, I am trying to do a bit more with it.
I am going to re direct IQ samples to/from P30 instead of to/from NXP arm cpu, which will let me connect hackrf to another device.
Looking at sgpio_if/top.vhd, my initial feeling suggested me that I might be able to get it done by changing HOST_DATA and CODEC_X2_CLK pin assignment in ucf file at initial step. (due to my vhdl knowledge almost doesn't exist, this is a quickest way for now)
entity top is    Port(        HOST_DATA       : inout std_logic_vector(7 downto 0);        HOST_CAPTURE    : out   std_logic;        HOST_DISABLE    : in    std_logic;        HOST_DIRECTION  : in    std_logic;        HOST_DECIM_SEL  : in    std_logic_vector(2 downto 0);        HOST_Q_INVERT   : in    std_logic;                   DA              : in    std_logic_vector(7 downto 0);        DD              : out   std_logic_vector(9 downto 0);
        CODEC_CLK       : in    std_logic;        CODEC_X2_CLK    : in    std_logic               );

So, I loaded sgpio_if project in xilinx ISE webpack 14.1 and removed temporary generated files and finally re built/generated programming file. But, I did not see default.xsvf file. In order to load cpld image onto cpld, I need it. Obviously, I missed some steps here.
If anyone here have done so or know how to do so, could you please let me know? also, any advice is welcome.
Cheers,Louie 		 	   		  
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